Title:
【発明の名称】SOIウエハ上の下地絶縁体層の上のシリコン・デバイス層にシリコンの複数の薄いデバイス・メサを形成する方法
Document Type and Number:
Japanese Patent JP2737808
Kind Code:
B2
Abstract:
A method of forming a SOI integrated circuit includes defining thin silicon mesas by etching a device layer down to the underlying insulator, forming a nitride bottom polish stop in the bottom of the apertures by a low temperature PECVD process, with nitride sidewalls on the silicon mesas being susceptible to easy removal, so that no hard material is present during a chemical-mechanical polishing step to thin the device layer down to less than 1000 ANGSTROM , and filling the apertures with a temporary layer of polysilicon to provide mechanical support to the edges of the device layer during the polishing operation.
Inventors:
BINDARU AAMAA
GARII KYARORU
ROEDO NIIIUO
GARII KYARORU
ROEDO NIIIUO
Application Number:
JP51411394A
Publication Date:
April 08, 1998
Filing Date:
May 18, 1993
Export Citation:
Assignee:
INTAANASHONARU BIJINESU MASHIINZU CORP
International Classes:
H01L21/304; H01L21/306; H01L21/321; H01L21/76; H01L21/762; H01L27/12; (IPC1-7): H01L21/762; H01L21/304; H01L27/12
Domestic Patent References:
| JP3250750A | ||||
| JP63250853A |
Attorney, Agent or Firm:
Kiyoshi Goda (2 outside)