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Patent Searching and Data


Title:
IC PACKAGE
Document Type and Number:
Japanese Patent JPS5877251
Kind Code:
A
Abstract:

PURPOSE: To erase actually the effect of inductance at a lead part, and to remove voltage variation of an electric power source terminal according to the action of an LSI itself by a method wherein a capacitor is built in according to a proper method between stitches for electric power source terminal and for earthing in a package.

CONSTITUTION: A chip type capacitor 4 is provided between an electric power source pad VDD and an earthing pad VSS, and electrodes of the capacitor 4 and stitches of a package are connected with solder 5. Although an electric power source current varies as usual according to action of an LSI 6 itself, it is absorbed by the capacitor 4, and variation of current to appear in inductance becomes to extremely small. Accordingly, voltage variation to appear between electric power source terminals of LSI chip becomes small, and stable action can be attained.


Inventors:
KACHI YOSHIO
Application Number:
JP17603481A
Publication Date:
May 10, 1983
Filing Date:
November 02, 1981
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L25/00; H01L21/822; H01L23/64; H01L27/04; (IPC1-7): H01L25/04; H01L27/02
Attorney, Agent or Firm:
Uchihara Shin