Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
IDENTIFICATION CIRCUIT FOR TERNARY LEVEL SIGNAL
Document Type and Number:
Japanese Patent JPS63232515
Kind Code:
A
Abstract:

PURPOSE: To attain the compatibility of the simple constitution of a circuit and the accurate identification of pulses by utilizing an output from a comparator so as to control a threshold.

CONSTITUTION: At first, a constant-voltage VB is adjusted in +VTH which is higher than the zero level of inputted ternary level signal. When the ternary level signal S is inputted in an input 11 and crosses with the threshold VTH, the non-inversion output 13 of the comparator 2 outputs the one of binary level signals at the first transition of the input signals S. Meanwhile, since an inversion output 14 outputs the zero level, the voltage is composed with Vb to alter the threshold to -VTH, which is supplied to an input 12. When the input ternary signal S rises, the non-inversion output 13 of the comparator 2 outputs the zero of the binary level signal and the voltage equal to one level occurs in the inversion output 14, then the threshold voltage alters to +VTH. Thus, a ternary/binary conversion circuit having little distortion of pulse width can be obtained in the extremely simple constitution of the circuit.


Inventors:
FUKUOKA TAKASHI
Application Number:
JP6528087A
Publication Date:
September 28, 1988
Filing Date:
March 19, 1987
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
SUMITOMO ELECTRIC INDUSTRIES
International Classes:
H03K3/0233; H03K3/023; H03K5/01; H03K5/08; H04L25/03; H04L25/49; (IPC1-7): H03K3/023; H03K5/01; H04L25/03; H04L25/49
Attorney, Agent or Firm:
Takashi Koshiba