To improve the response between the output of instruction and the start of operation by efficiently collating identification codes.
This device is composed of a device 1 to be detected and a detector 3. The detector 3 has a storage section 12 and a collection section 18 that collates a specific identification code (IDS) of a received signal with a registered identification code (IDR) read from the storage section 12, and a processing control section 11. Each of the identification codes consists of plural blocks respectively in a prescribed bit number, and is hierarchically blocked especially for the entire IDR. The processing control section 11 controls the collation section 18 to collate both the codes as to the same block, and when the IDR at a block agrees with the IDS, a succeeding IDR to be collated is specified, and the collation control between the concerned blocks and the specification of a succeeding IDR are repeated while the collated block is being changed from, e.g. a higher-order bit until the collation of all the blocks is finished.
TAKAMATSU HIROYUKI
TAMURA MITSUYASU
