PURPOSE: To execute the processing at a high speed by providing a communication control use interface (CCI) circuit for relaying the transmission/reception of information between an image forming device body and an additional device.
CONSTITUTION: The CCI circuit is constituted of a bus buffer 250 for inputting and outputting the data D0WD7 to and from a CPU, an address decoder 251 for inputting an address data, etc., an internal register 252, and transmitting/ receiving blocks 255W258, etc. In such a state, a data from the CPU is sent directly to the transmitting/receiving blocks 255W258 of each channel from the buffer 250, and a received data by each block is transferred to the CPU through only a multiplexer circuit 253, therefore, there is scarcely a signal delay time extending from an external bus to the inside. Also, data of each block 255W258 and the internal register 252 are always inputted to the circuit 253, a delay time extending from the active of a read signal RD to a data output is only a gate delay time in the circuit 253, and a write timing is also the same. Accordingly, a data is transmitted and received by a high frequency to and from the CPU, and a communication speed is increased and high speed processing can be executed.
YAMAZAKI SHIGERU
YAMANOBE KOJI
KOTABE HIROAKI
NAKAZATO YASUFUMI
AZENO MASAHIKO
| JPS5821268A | 1983-02-08 | |||
| JPS60188781A | 1985-09-26 |