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Title:
IMAGE PROCESSING CIRCUIT BASED ON MULTILEVEL INFORMATION
Document Type and Number:
Japanese Patent JP2000207537
Kind Code:
A
Abstract:

To simplify an arithmetic circuit and to attain improvement in the density of integration by operating multilevel information from plural pixels and performing processing such as the edge detection, reduction or expansion of an image.

Respective currents from pixels C and G are applied to terminals 24 and 30 of an image edge detecting circuit and the current applied to that terminal 24 is copied by a current mirror composed of P channel MOS transistors (PFET) 21, 22 and 23, and outputted by the PFET 22 and 23. Similarly, the current applied to the terminal 30 is copied by a current mirror composed of PFET 27, 28 and 29, and outputted by the PFET 28 and 29 so that the precise edge detection is enabled. Thus, when the image edge is detected between the pixels C and G, the output current is obtained at the terminal 37 or 39 and a current difference thereof can be provided by operating the multilevel information.


Inventors:
IGARASHI MAKOTO
Application Number:
JP4045799A
Publication Date:
July 28, 2000
Filing Date:
January 08, 1999
Export Citation:
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Assignee:
IGARASHI MAKOTO
International Classes:
G06G7/48; G06T1/00; G06T1/20; G06T7/60; G06T9/20; G09G5/36; G09G5/373; (IPC1-7): G06T1/00; G06T9/20; G06G7/48; G09G5/373