To execute a decode processing with a plurality of decode chips by dividing a decode range.
Since a motion search range of each macro block included in a first area of a P picture decoded by a #1 decode chip corresponds to an area included in a search range of a motion vector in the decode processing of the #1 decode chip among pieces of pixel data of a first area and a second area of an I picture and a motion search range of each macro block included in the second area of the P picture decoded by a #2 decode chip corresponds to an area included in the search range of the motion vector in the decode processing of the #2 decode chip among the pieces of pixel data in the second area and the first area of the I picture, the #1 decode chip and the #2 decode chip preliminarily supply pixels in areas referred to by other decode chips to other decode chips. This invention is applicable to a decoder.
OHASHI MASAKAZU
MITANI KOICHI
KONO SHIGEO
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