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Title:
IMPEDANCE MEASURING DEVICE
Document Type and Number:
Japanese Patent JP2008157911
Kind Code:
A
Abstract:

To certainly cancel an error generated in a signal conversion circuit contained in input system of a measuring signal, while measuring simultaneously a voltage signal and a current signal which are obtained from a sample to be measured.

When each of the voltage signals and the current signals obtained from the sample to be measured is converted into a predetermined signal form by the signal conversion circuit and is given to a control means, then an impedance of the sample to be measured is to be obtained, the device has two signal conversion circuits 100 and 200 of the same configuration and has switches SW1 and SW2 which switch each signal conversion circuit into a voltage signal input channel 1 and a current signal input channel 2. As a first step, the signal conversion circuit 100 is connected to the voltage signal input channel 1 and the signal conversion circuit 200 is connected to the current signal input channel 2, then the impedance Z1 is calculated. As the second step, the signal conversion circuit 100 is connected to the current signal input channel 2 and the signal conversion circuit 200 is connected to the voltage signal input channel 1, then the impedance Z2 is calculated. The impedance Z of the sample to be measured is obtained from the impedances Z1, Z2.


Inventors:
TERAJIMA TAKAYUKI
YAMAGUCHI TSUTOMU
TAGUCHI KEIICHI
Application Number:
JP2007162559A
Publication Date:
July 10, 2008
Filing Date:
June 20, 2007
Export Citation:
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Assignee:
HIOKI ELECTRIC WORKS
International Classes:
G01R27/02
Domestic Patent References:
JP2001201524A2001-07-27
Attorney, Agent or Firm:
Takuya Ohara