Title:
IMPROVED INTEGRATED CIRCUIT CHIP PACKAGING METHOD
Document Type and Number:
Japanese Patent JPH10163237
Kind Code:
A
Abstract:
To reduce time and consumption power for manufacturing an integrated circuit chip package.
An integrated circuit chip 12 is mounted on a lead frame 18 having a plurality of leads 20. This integrated circuit chip is electrically connected with a lead frame by using bonding wires 22. Encapsulating material 26 is molded around the integrated circuit chip and the lead frame. In a dry bake step, moisture is eliminated from the encapsulating material 26, for dry carriage of the integrated circuit chip after molding stage. At the same time as the dry bake step, the encapsulating material 26 is cured. Thereby time and power necessary for manufacturing an integrated circuit chip package can be reduced.
Inventors:
ZUNIGA EDWARD R
HELMICK MARY E
HELMICK MARY E
Application Number:
JP32103097A
Publication Date:
June 19, 1998
Filing Date:
November 21, 1997
Export Citation:
Assignee:
TEXAS INSTRUMENTS INC
International Classes:
H01L21/50; H01L21/56; (IPC1-7): H01L21/56; H01L21/50
Attorney, Agent or Firm:
Minoru Nakamura (6 outside)
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