Title:
IMPROVED MEMORY DEVICE
Document Type and Number:
Japanese Patent JPS5771591
Kind Code:
A
Abstract:
A memory device is provided for an integrated injection logic (I2L) device in solid state form by a resistor connected at one end to the logic device, and a diode having its cathode connected to the other end of the resistor at a programming junction, and its anode connected to a common point. If the diode conductors are melted or deformed by reverse diode current from the programming junction to the common point, a low impedance path is formed, and the logic portion is provided with a first logic input. If the diode conductors are left unmelted or intact, the logic portion is provided with a second logic input.
Inventors:
RICHIYAADO JIYON PATSUCHI
JIYOOJI DANIERU ROOZU JIYUNIA
JIYOOJI DANIERU ROOZU JIYUNIA
Application Number:
JP13221881A
Publication Date:
May 04, 1982
Filing Date:
August 25, 1981
Export Citation:
Assignee:
GEN ELECTRIC
International Classes:
G11C17/06; G11C17/16; H01L23/525; H01L27/02; H03K19/091; (IPC1-7): G11C11/40; G11C17/00
Previous Patent: 給紙装置、およびこれを備えた画像読取装置、画像形成装置
Next Patent: ADDRESS BUFFERING CIRCUIT OF ROM(READ-ONLY MEMORY)
Next Patent: ADDRESS BUFFERING CIRCUIT OF ROM(READ-ONLY MEMORY)