Title:
情報処理装置、イジング装置及び情報処理装置の制御方法
Document Type and Number:
Japanese Patent JP6623947
Kind Code:
B2
Abstract:
Arithmetic circuits calculate d−1 energy values (hi2 to hid) indicating energies generated by 2-body to d-body coupling on the basis of a plurality of weight values indicating strength of 2-body to d-body coupling of 2 to d neurons including a first neuron whose output value is allowed to be updated and n-bit output values of n neurons. An adder circuit calculates a sum of these values, and a comparator circuit compares a value based on a sum of the sum and a noise value with a threshold, to determine the output value of the first neuron. An update circuit outputs n-bit updated output values in which one bit has been updated on the basis of a selection signal and the output value of the first neuron. The holding circuit holds the updated output values and outputs the updated output values as the n-bit output values used by the arithmetic circuits.
Inventors:
Tashi David
Yasutaka Tamura
Zoka Tsukamoto
Yasutaka Tamura
Zoka Tsukamoto
Application Number:
JP2016120717A
Publication Date:
December 25, 2019
Filing Date:
June 17, 2016
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06G7/122; G06G7/60
Domestic Patent References:
| JP4078978A | ||||
| JP2027493A | ||||
| JP7200512A | ||||
| JP62295186A |
Attorney, Agent or Firm:
Takeshi Hattori