Title:
情報処理装置及びその制御方法並びにプログラム
Document Type and Number:
Japanese Patent JP7195941
Kind Code:
B2
Abstract:
An information processing apparatus that is capable of reducing deviation of cycles of modules having independent clock supply sources. A processor controls a first module to operate in synchronization with a first synchronizing signal supplied from a first timing controller, controls a second module to operate in synchronization with a second synchronizing signal supplied from a second timing controller, measures times of supplying the synchronizing signals to the modules, calculates a time difference between the times when the first timing controller is switched to a second mode where the first synchronizing signal is supplied to the first module based on a setting period after synchronizing the synchronizing signals in a first mode where the first synchronizing signal is supplied to the first module in synchronization with the second synchronizing signal, and changes the setting period when the time difference is more than a threshold.
Inventors:
Atsushi Ito
Application Number:
JP2019004342A
Publication Date:
December 26, 2022
Filing Date:
January 15, 2019
Export Citation:
Assignee:
Canon Inc
International Classes:
H04N5/232; H04L7/00; H04N5/369
Domestic Patent References:
| JP5631084B2 | ||||
| JP2011015221A |
Foreign References:
| US20170085755 |
Attorney, Agent or Firm:
Another role