Title:
クロック生成回路を備えた情報処理装置およびクロック遅延回路を備えた情報処理装置
Document Type and Number:
Japanese Patent JP4071604
Kind Code:
B2
Abstract:
An information-processing device comprises a circuit (10) producing an internal clock signal (PLL-OUT) from an oscillation of a clock signal (N-OUT) which is equal to or a multiple of (20) a reference (REF.CLK) and a control (12) setting an initial value. The clock circuit has a counter and an oscillation circuit gives the clock signal. An Independent claim is also included for a circuit as above having a clock delay circuit.
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Inventors:
Koichi Iwami
Application Number:
JP2002334116A
Publication Date:
April 02, 2008
Filing Date:
November 18, 2002
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G06F1/04; H03L7/081; G06F1/08; H03K5/00; H03K5/13; H03L7/07; H03L7/08; H03L7/087; H03L7/099
Domestic Patent References:
| JP2001211070A | ||||
| JP10341156A | ||||
| JP2000244309A | ||||
| JP11177399A | ||||
| JP11041095A | ||||
| JP8016276A | ||||
| JP7123000A |
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai