Title:
情報処理システム、情報処理装置、及び情報処理システムの制御方法
Document Type and Number:
Japanese Patent JP6853479
Kind Code:
B2
Abstract:
An information processing system includes: a processor in one information processing apparatus among information processing apparatuses coupled via a ring bus corresponding to a closed-loop bus; and a first memory, wherein the processor: generate a verification request for verification of completion of a write request after issuing the write request to a second memory in the information processing apparatuses; transmit the verification request to a subsequent information processing apparatus; transmit, when a request from a preceding information processing apparatus is not a verification request, the request to the subsequent information processing apparatus; transmit, when the request is a verification request to another information processing apparatus, the verification request and a request to the first memory to the subsequent information processing apparatus in order of receiving; and execute, when the request is a verification request to the one information processing apparatus, processing and generate a response of completion of the processing.
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Inventors:
Atsushi Kawahara
Masaki Kusita
Masaki Kusita
Application Number:
JP2017131270A
Publication Date:
March 31, 2021
Filing Date:
July 04, 2017
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F13/38; G06F13/36
Domestic Patent References:
| JP2004158000A | ||||
| JP2007148753A | ||||
| JP2008066971A |
Foreign References:
| US20180083827 | ||||
| WO2007105373A1 |
Attorney, Agent or Firm:
Takayoshi Kokubun