To provide an information processor having a flash memory which when one bit of data is inverted in a certain address of the flash memory detects the errorneous bit and is capable of releaving the data by automatically correcting a faulty sector or by automatically changing a sector mapping.

This device is provided with a flash memory 11 in which the reading/writing of data is performed while storage areas are managed by a sector and an error detecting circuit 13 detecting the position of an error bit in read data based on redundant data when data including the redundant data are read out from the certain sector. Then, the device generates data in which the errorneous bit of the read data is corrected in accordance with the position of the errorneous bit detected by the error detecting circuit 13 and rewrites the data in original sector from which the errorneous data are read out or assignes vacant sectors 11e, 11f, in the flash memory 11 as substitutive sectors of the sector from which the errorneous bit is generated to write the corrected data in the vacant sectors 11e, 11f.