PURPOSE: To suppress the disturbance of a pipeline at its minimum and to reduce the quantity of hardwares by controlling the pipeline in accordance with previously determined priority at the time of detecting the competition of updating requests outputted from plural stages of the pipeline.

CONSTITUTION: When a competition detecting part 8 detects the competition of updating requests outputted from plural stages (an operation part and a preceding control part), selecting circuits 12 to 14 are controlled in accordance with the previously determined priority and a register group 1 is updated by updating request data obtained from the operation part. At that time, the updating request to be waited at its updating is receded in a receding buffer 6, and new updating requests are not generated from the plural stages, the selecting circuits 12 to 14 are controlled and the register group 1 is updated by the updating request receded in the buffer 6. Consequently, the disturbance of the pipeline can be suppressed at its minimum and only one register group in the preceding control part is used, the quantity of hardwares can be reduced.