PURPOSE: To prevent the processing delay of a CPU that is caused by the occurrence of an interruption by controlling the register holding the data processed with a program into a data store inhibiting state out of plural registers at occurrence of the interruption and at the same time outputting the data of the inhibited register for execution of a due process when the interruption is reset.

CONSTITUTION: An information processor includes the register groups 1a - 1m, the selectors 3a - 3m, an interruption processing part 5, and a paging control part 7. When an interruption occurs during execution of a program, the writing operation is inhibited to the register group that holds the data processed by the program among those groups 1a - 1m. When the interruption is reset, the data on the register whose writing operation is inhibited is supplied to the selectors 3a - 3m. Based on this data, the program is carried out. Thus it is possible to prevent the delay of the CPU processing time due to the occurrence of an interruption.