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Patent Searching and Data


Title:
INFORMATION PROCESSOR
Document Type and Number:
Japanese Patent JPS5829055
Kind Code:
A
Abstract:

PURPOSE: To reduce readout and write time of information to a processor at diagnosis, by detecting the number of bits of FF groups with one access and storing the number to a storage circuit.

CONSTITUTION: A flip-flop group FFM selected in a processor is shifted with a clock signal CM and the content of FFM0WFFMK-1 is appeared in a scanout signal SoutM as a time series. The signal SoutM is selected at a switching circuit 5 and applied to a storage circuit 5 of a diagnostic control section 4. When the signal Sout is written in the circuit 5, the content of an address register 8 is added by 1 and the content of the FFM is shifted right by one bit. On the other hand, the content of a storage circuit 6 corresponding to each set of the FF group and the content of the register 8 are compared at a coincidence circuit 7 and this operation is repeated until the result of comparison is coincident with each other. The content of the address of the circuit 5 designated at the register 8 is applied to the processor with a scan-in signal Sin and the content of the FFM is shifted.


Inventors:
NISHINA RIYOUZOU
Application Number:
JP12809981A
Publication Date:
February 21, 1983
Filing Date:
August 15, 1981
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
G06F11/22; G01R31/3185; (IPC1-7): G06F11/22
Attorney, Agent or Firm:
Yutaro Kumagai