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Patent Searching and Data


Title:
INFORMATION PROCESSOR
Document Type and Number:
Japanese Patent JPS5860482
Kind Code:
A
Abstract:

PURPOSE: To eliminate unnecessary writing to a cash memory by deciding on whether writing from a main storage device to the cash memory is performed or not in response to a write indication queuing indication and an indication for showing whether a branch instruction has been executed or not.

CONSTITUTION: When a host address of an actual address from the advance control part 2 of a processor 10 does not coincide with a host address of an aclual address of a block in a cash memory (CM), a comparing circuit 5 sends a block transfer request to a main storage device (MM)6 and a bus 26 to a CM write indication queuing circuit 7 is held at a high level. On the other hand, a bus 22 is held at the high level in response to a request to read a branch instruction in a control part 2 to apply a high-level write indication queuing output from the circuit 7 to a CM write control circuit 8. In this state, when a branch success or failure indication is applied from starting execution control part 1, the circuit 8 responds to each indication to decide on whether writing is performed or not and only when the success in branching is obtained, writing from the MM 6 to the CM 4 is performed. Thus, information processing performance is improved without any unnecessary writing.


Inventors:
YAMANO KOUZOU
OOMORI YUUZOU
Application Number:
JP15831681A
Publication Date:
April 09, 1983
Filing Date:
October 05, 1981
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
G06F9/38; G06F12/08; (IPC1-7): G06F13/00; G11C9/06
Attorney, Agent or Firm:
Kusano Takashi