PURPOSE: To vary information tracing length by providing an information selector circuit and an address decoder circuit to operate plural memories as one memory in which respective addresses are continuing.

CONSTITUTION: Selecting circuits 22W24 are controlled so as to select respective input information S2WS4 and input the selected information to corresponding memories M2WM4. Consequently, respective memories M1WM4 operate as four memories enabled to trace the respectively different input information S1WS4 for n clocks. When the information tracing length is twice length, outputs 101W104 are outputted from the address decoder circuit 100 so that the memories M1WM4 are acted as two pairs of memories M1, M2 and M3, M4 of which number of words is 2n and information for 2n clocks can be respectively traced. When the information tracing length is four-times length, outputs 101W104 are outputted from the address decoder circuit 100 so that the memories M1WM4 are acted as one memory of which the number of words is 4n and information for 4n clocks can be traced.