Title:
INPUT BUFFER CIRCUIT
Document Type and Number:
Japanese Patent JP3413445
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent the increase of the number of pins because of the need of setting special pins for testing, namely, so-called idle pins which are not actually used to test highly accurate and multifunctional LSIs.
SOLUTION: By adding a simple circuit like a current mirror circuit to an external terminal 2 to which an input buffer 10 is led out, a normal digital input pin can serve also as a current source connecting pin for testing. At normal use time, an extra current is prevented from flowing to a circuit 4 for testing. Oppositely, since an input signal to an internal circuit 3 is normally fixed at a current supply time to the circuit 4 for testing, a malfunction can be prevented. Moreover, switching between the normal use time and the test use time is dependent only on an input to the external terminal 2, and a special input signal or another terminal for the switching is effectively eliminated.
Inventors:
Masaki Tsujimoto
Application Number:
JP33403599A
Publication Date:
June 03, 2003
Filing Date:
November 25, 1999
Export Citation:
Assignee:
NEC Electronics Corporation
International Classes:
G01R31/28; H01L21/822; H03K19/00; H01L27/04; H03K19/0175; (IPC1-7): G01R31/28; H03K19/00; H03K19/0175
Domestic Patent References:
| JP6342484A | ||||
| JP1166890A |
Attorney, Agent or Firm:
Masahiko Desk (2 outside)