PURPOSE: To decrease the number of wires of gate input terminals by arranging NAND gates dispersedly at an input and an output side.

CONSTITUTION: The NAND gates 16∼19 form RS type FFs 13 and 14, whose outputs -Q1 and -Q2 are connected to a binary input terminal of an MPX29. A table 1 shows which of outputs Q1 and Q2 and output terminals 9, 10, 11, and 12 are at a level L when switches (SW)1, 2, 3, or 4 is pressed. For example, when the SW1 is pressed, the -Q1 and -Q2 are at L and the Q1 and Q2 are at H, which is held. Thus, when one of the SWs is pressed, binary data indicating which SW is pressed appear at the outputs Q1 and Q2, or -Q1 and -Q2. Consequently, one of outputs of gates 20∼23 goes down to L corresponding to the pressed SW as shown in the table. For example, when the SW1 is pressed, only a light emitting diode 9 turns on. Then, the outputs of the gates 17 and 19 are applied to the MPX29, one of input terminals 24∼27 is connected to an output terminal 28 corresponding to the SW.