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Patent Searching and Data


Title:
INPUT SIGNAL CUT DETECTION DEVICE
Document Type and Number:
Japanese Patent JPH06311111
Kind Code:
A
Abstract:

PURPOSE: To prevent malfunction accompanied by circuit noise by detecting that a periodical signal is not inputted based on a difference between an input signal and an output signal from a delay means.

CONSTITUTION: The delay circuit 21 delays the clock pulse of a period Ts, which is outputted from a limitter amplifier circuit 303 by a (n+2/4) period, and inputs it to the clock input terminal C of a D-flip flop FF22. The clock pulse outputted from the circuit 303 is inputted to an input terminal D. The output value of the circuit 303 at a moment when the output of the circuit 21 rises is always outputted based on the difference between the input signal and the output signal of the circuit 21. Here, a detection means detects that the periodical signal is not inputted to D-FF 22, and outputs an input signal cut detection signal from a NAND circuit 29. Thus, the malfunction accompanied by circuit noise is prevented and malfunction can be prevented even if whisker occurs with the input of the signal of a high speed bit rate.


Inventors:
YASUDA AKIHIKO
Application Number:
JP9350593A
Publication Date:
November 04, 1994
Filing Date:
April 21, 1993
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04B1/10; H04B10/07; H04B10/079; H04B10/2507; (IPC1-7): H04B10/08; H04B1/10; H04B10/18
Attorney, Agent or Firm:
Hattori Takeshi