Title:
検査条件設定プログラム、検査装置および検査システム
Document Type and Number:
Japanese Patent JP4126189
Kind Code:
B2
Abstract:
A program is provided for setting efficiently, and with precision, the inspection conditions of an inspection device that detects particles and deformed patterns in or on products such as semiconductor integrated circuits that are manufactured by simultaneously forming a plurality of products on a single substrate. In particular, the system achieves greater efficiency of the setting of cell comparison regions and the setting of non-inspection regions. Input processing of a product type code, input processing of chip size and configuration information, reading processing of circuit layout data, extraction processing of repeated pattern region coordinates, extraction processing of sparse region coordinates and circuit pattern condition registration processing are sequentially executed.
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Inventors:
Makoto Ono
Youhei Asakawa
Naofumi Iwata
Kanako Harada
Youhei Asakawa
Naofumi Iwata
Kanako Harada
Application Number:
JP2002107284A
Publication Date:
July 30, 2008
Filing Date:
April 10, 2002
Export Citation:
Assignee:
Hitachi High-Technologies Corporation
International Classes:
G01N21/956; H01L21/66; G01R31/303; G06T1/00; G06T7/00; H01L21/00
Domestic Patent References:
| JP200335680A | ||||
| JP11166908A | ||||
| JP62269046A |
Attorney, Agent or Firm:
Manabu Inoue
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