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Title:
INSTRUCTION DECODING CIRCUIT
Document Type and Number:
Japanese Patent JPS6272033
Kind Code:
A
Abstract:

PURPOSE: To improve the efficiency of a program memory by decoding only one instruction placed right behind an instruction with skip conditions.

CONSTITUTION: An instruction outputted by an instruction register 1 is decoded by an instruction decoder 4 and an instruction detecting means 2 decides whether or not it is an instruction with skip conditions. When so, the instruction detecting means 2 outputs a reset signal after the operation of the instruction decoder 4 to set a flip-flop 3. Consequently, the instruction decoder 4 is made invalid and an instruction decoder 4' is made valid. When a next instruction is outputted by the instruction register 1 in this state, the instruction is decoded by the instruction decoder 4'. A reset signal is outputted to the flip-flop 3 at the end of the operation of the instruction decoder 4' to make the instruction decoder 4 valid and the instruction decoder 4' invalid, respectively.


Inventors:
SAWADA AKIRA
Application Number:
JP21282785A
Publication Date:
April 02, 1987
Filing Date:
September 25, 1985
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F9/30; G06F9/32; (IPC1-7): G06F9/30; G06F9/32
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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