PURPOSE: To fetch an instruction at a high speed with use of a high speed access mode of a dynamic memory.

CONSTITUTION: An instruction fetch control pert 10 decodes an instruction fetch control field in an instruction if this instruction is not equal to a branch instruction. Then the part 10 decides whether a high speed access mode is usable for the next instruction fetch or not and informs a memory access control part 4 of this deciding result. If a branch instruction is confirmed, an instruction decoding part 6 decodes a branch destination instruction fetch control field in an instruction and decides whether the high speed access mode is usable or not for the instruction fetch to the branch destination. Then the part 8 informs the part 4 of the deciding result. Therefore it is not required to perform the comparison of row addresses after the output of an instruction fetch address.