Title:
命令オペコード生成システム
Document Type and Number:
Japanese Patent JP5218063
Kind Code:
B2
Inventors:
Takahiro Hisamura
Application Number:
JP2008545398A
Publication Date:
June 26, 2013
Filing Date:
November 19, 2007
Export Citation:
Assignee:
NEC
International Classes:
G06F9/30; G06F17/50
Other References:
JPN7012003466; Ａｃｈｉｍ Ｎｏｈｌ ｅｔ ａｌ．: 'Ｉｎｓｔｒｕｃｔｉｏｎ Ｅｎｃｏｄｉｎｇ Ｓｙｎｔｈｅｓｉｓ ｆｏｒ Ａｒｃｈｉｔｅｃｔｕｒｅ Ｅｘｐｌｏｒａｔｉｏｎ ｕｓｉｎｇ Ｈｉｅｒａｒｃｈｉｃａｌ Ｐｒｏｃｅｓｓｏｒ Ｍｏｄｅｌｓ' ＤＡＣ ０３ Ｐｒｏｃｅｅｄｉｎｇｓ ｏｆ ｔｈｅ ４０ｔｈ ａｎｎｕａｌ Ｄｅｓｉｇｎ Ａｕｔｏｍａｔｉｏｎ Ｃｏｎｆｅｒｅｎｃｅ , 20030606, ｐｐ．２６２-２６７, ＡＣＭ
JPN6012043689; Ｌ． Ｂｅｎｉｎｉ ｅｔ ａｌ．: 'Ａｕｔｏｍａｔｉｃ ｓｅｌｅｃｔｉｏｎ ｏｆ ｉｎｓｔｒｕｃｔｉｏｎ ｏｐ-ｃｏｄｅｓ ｏｆ ｌｏｗ-ｐｏｗｅｒ ｃｏｒｅ ｐｒｏｃｅｓｓｏｒｓ' ＩＥＥ Ｐｒｏｃｅｅｄｉｎｇｓ Ｃｏｍｐｕｔｅｒｓ ＆ Ｄｉｇｉｔａｌ Ｔｅｃｈｎｉｑｕｅｓ Ｖｏｌ １４６，Ｉｓｓｕｅ ４, 199907, ｐｐ．１７３-１７８, ＩＥＥＥ
JPN6012043689; Ｌ． Ｂｅｎｉｎｉ ｅｔ ａｌ．: 'Ａｕｔｏｍａｔｉｃ ｓｅｌｅｃｔｉｏｎ ｏｆ ｉｎｓｔｒｕｃｔｉｏｎ ｏｐ-ｃｏｄｅｓ ｏｆ ｌｏｗ-ｐｏｗｅｒ ｃｏｒｅ ｐｒｏｃｅｓｓｏｒｓ' ＩＥＥ Ｐｒｏｃｅｅｄｉｎｇｓ Ｃｏｍｐｕｔｅｒｓ ＆ Ｄｉｇｉｔａｌ Ｔｅｃｈｎｉｑｕｅｓ Ｖｏｌ １４６，Ｉｓｓｕｅ ４, 199907, ｐｐ．１７３-１７８, ＩＥＥＥ
Attorney, Agent or Firm:
Michio Nagai
Masao Sekiguchi
Takamasa Nakano
Masao Sekiguchi
Takamasa Nakano
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