Title:
INSTRUCTIONS TO MARK BEGINNING AND END OF NON-TRANSACTIONAL CODE REGION REQUIRING WRITE BACK TO PERSISTENT STORAGE
Document Type and Number:
Japanese Patent JP2014182836
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a processor which identifies cache lines to be persistently saved in non-volatile random access memory.SOLUTION: A processor 100 comprises an interface to non-volatile random access memory and logic circuitry. The logic circuitry identifies cache lines modified by a transaction which views the non-volatile random access memory as the transaction's persistence storage. The logic circuitry also identifies cache lines modified by a software process other than a transaction that also views the non-volatile random access memory as persistence storage.
Inventors:
THOMAS WILLHALM
Application Number:
JP2014052025A
Publication Date:
September 29, 2014
Filing Date:
March 14, 2014
Export Citation:
Assignee:
INTEL CORP
International Classes:
G06F12/08; G06F9/30; G11C13/00
Domestic Patent References:
| JP2009527866A | 2009-07-30 | |||
| JP2009501366A | 2009-01-15 | |||
| JP2009537053A | 2009-10-22 | |||
| JP2011154547A | 2011-08-11 |
Foreign References:
| WO2012040742A2 | 2012-03-29 | |||
| US20110167222A1 | 2011-07-07 | |||
| WO2009122694A1 | 2009-10-08 |
Attorney, Agent or Firm:
Ryuka international patent business corporation
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