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Title:
INSULATED-GATE FIELD-EFFECT TRANSISTOR
Document Type and Number:
Japanese Patent JPS63147373
Kind Code:
A
Abstract:

PURPOSE: To obtain an MISFET capable of controlling a threshold voltage at a desired value by a method wherein high-concentration semiconductor layers are formed in the vicinities of both ends of the lower part of a gate electrode and a source electrode and a drain electrode are formed on the high-concentration semiconductor layers.

CONSTITUTION: A high-purity GaAs layer 2 having a constant electron affinity is formed on a semi-insulating GaAs substrate 1 and a high-purity AlGaAs layer 3 having an electron affinity smaller than that of the GaAs layer 2 is formed in such a way as to come into contact to the upper surface of the GaAs layer 2. Moreover, a gate electrode 4 for controlling carriers to be formed in the above GaAs layer 2 is formed on the AlGaAs layer 3, high-concentration semiconductor layers 5 are formed on the GaAs layer 2 and in the vicinity of both ends of the lower part of the gate electrode and a source electrode 6 and a drain electrode 7 are provided on the high- concentration semiconductor layers 5. A threshold voltage is so contrived as to be controlled according to a gate length to be formed. The above high-concentration semiconductor layers 5 are formed by a method wherein an ion-implantation of Si is performed using the gate electrode 4, for example, as a mask and an annealing treatment is performed.


Inventors:
SUZUKI YASUYUKI
Application Number:
JP29534086A
Publication Date:
June 20, 1988
Filing Date:
December 10, 1986
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L29/78; H01L21/338; H01L29/778; H01L29/80; H01L29/812; (IPC1-7): H01L29/78; H01L29/80
Attorney, Agent or Firm:
Uchihara Shin



 
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