Title:
INSULATING GATE BIPOLAR TRANSISTOR AND ITS MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP3206289
Kind Code:
B2
Abstract:
PURPOSE: To improve latch-up withstanding strength that is regarded as a weak point in an insulating gate bipolar transistor with a vertical-type structure.
CONSTITUTION: An n-type source layer 23, for example, is diffused inside a p-type base layer 22 that has been diffused from a surface of an n-type semiconductor region 12. After a recessed part 24 that reaches a semiconductor region 12 is drilled from the surface of the source layer 23 through the base layer 22, an insulating gate 25 is buried therein. A p-type collector layer 26 is diffused from the semiconductor region 12 on the opposite side to the insulating gate 25 in the source layer 23. Then, holes (h), which are produced by electrons (e) flowing into the collector layer 26, are taken out from a contact layer 27 of the base layer 22 to an emitter terminal (E). In addition, while the holes (h) pass sideways through the base layer 22 under the source layer 23, the holes (h) are injected into the source layer 23 so that latch-up affected from the holes (h) is prevented.
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Inventors:
Hitoshi Sumita
Application Number:
JP7521794A
Publication Date:
September 10, 2001
Filing Date:
April 14, 1994
Export Citation:
Assignee:
Fuji Electric Co., Ltd.
International Classes:
H01L29/78; (IPC1-7): H01L29/78
Domestic Patent References:
| JP5206159A | ||||
| JP62189758A | ||||
| JP479376A | ||||
| JP2224274A |
Other References:
【文献】欧州特許出願公開526939(EP,A1)
Attorney, Agent or Firm:
Masaharu Shinobe