Title:
INTEGRATED CIRCUIT FOR DETECTING DEFECT OF TEST BOARD OF SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3114655
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To correctly detect erroneous wiring and the like of a test board in a short time by inputting a signal to an optional input-output terminal, and comparing signals output from a plurality of specific terminals with an expected value.
SOLUTION: At first by inputting a low (L) level signal to the whole input- output terminals 1-8, output of the FF 21-28 of the output steps of the whole terminals 1-8 are held in the L-level. At this time, output of the FF 21-28 become the high impedance state. Next, by inputting a high (H) level signal to the terminal 1, output of the FF 26, 24 are inverted to the H-level, the H-level signals passed through the FF 29 and a delay circuit 30 are input to the enable terminals of the FF 21-28, and signals are output from the terminals 6, 4. The signals are compared with an expected value, and it is discriminated whether the wiring is correct or not. Similarly, against the whole terminals, an H-level signal is input to every terminal so as to carry out the test.
Inventors:
Masafumi Tanaka
Application Number:
JP15773397A
Publication Date:
December 04, 2000
Filing Date:
May 30, 1997
Export Citation:
Assignee:
NEC
International Classes:
G01R31/28; H01L21/822; H01L27/04; G01R31/02; (IPC1-7): G01R31/28; G01R31/02; H01L21/822; H01L27/04
Attorney, Agent or Firm:
Asamichi Kato