INTEGRATED CIRCUIT TESTING APPARATUS

Title:

INTEGRATED CIRCUIT TESTING APPARATUS

Document Type and Number:

Japanese Patent JPS60127475

Kind Code:

A

Abstract:

PURPOSE: To increase the setting and reducing speeds of the value of a circuit to be tested at a time when a logical circuit according to a scanning-in-and-out system, by forming a system latch into a tree shape.

CONSTITUTION: When a set value is applied to the scanning input I3 of a system latch S0 and a system clock is applied, a value is set to S0. In the next step, when control signals C0, C1 are set to "1, 0" while is applied, the value is set to S2 from S0 through I2. In addition, when signals C0, C1 are set to "0, 1" to apply , the value is set to "1,0" and is applied to S0, the value is read to S4 from S1 through I2. Next, when signals C0, C1 are set to "0,1" and is applied, the voltage is read to S6 from S4 through I1 and sent out to the outside from output Q.

Inventors:

TAMARU KIICHIROU

Application Number:

JP23456183A

Publication Date:

July 08, 1985

Filing Date:

December 13, 1983

Export Citation:

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Assignee:

TOSHIBA KK

International Classes:

G01R31/317; G06F11/267; H01L21/66; G01R31/28; H01L21/822; H01L27/04; (IPC1-7): G01R31/28; H01L21/66

Attorney, Agent or Firm:

Takehiko Suzue

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