Title:
フラッシュメモリデバイスを指定する集積回路
Document Type and Number:
Japanese Patent JP5879651
Kind Code:
B2
Abstract:
A system including a plurality of NAND flash memory devices each having a NAND flash interface, where the NAND flash interface of each NAND flash memory device includes an 8-bit data bus, and a memory controller configured to exchange data with the plurality of NAND flash memory devices via the 8-bit data bus. The memory controller is further configured to select a first NAND flash memory device of the plurality of NAND flash memory devices, without using a Chip Enable signal of the NAND flash interface, by transmitting, on the 8-bit data bus, an identification byte identifying the first NAND flash memory device. The memory controller is further configured to transmit, on the 8-bit data bus, a command byte to the first NAND flash memory device. The first NAND flash memory device is configured to perform an operation indicated by the command byte.
Inventors:
Urabe Masayuki
Application Number:
JP2012265696A
Publication Date:
March 08, 2016
Filing Date:
December 04, 2012
Export Citation:
Assignee:
Marvel World Trade Limited
International Classes:
G06F13/16; G06F12/00
Domestic Patent References:
| JP200184172A |
Foreign References:
| US20040148482 |
Attorney, Agent or Firm:
Longhua International Patent Service Corporation
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