Title:
低減された基板バウンスを有する集積回路
Document Type and Number:
Japanese Patent JP2005518699
Kind Code:
A
Abstract:
A clock strategy is provided for digital circuits inside mixed-signal ICs. An integrated circuit in accordance with the present invention comprises a plurality of pairs of latches (L 1 , L 2 ) being respectively clocked by two non-overlapping clock signals (Phi 1, Phi2 ). The clock strategy is aimed at keeping the substrate bounce caused by the digital circuits as low as possible. Preferably, not all latches are clocked at the same time, but delays are inserted in the clock lines so that the various latches do not consume current all at the same time. The invention relaxes the demands on the substrate sensitivity of the analog circuits.
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Inventors:
Juan Rammelen Johannes PM
Application Number:
JP2003570467A
Publication Date:
June 23, 2005
Filing Date:
January 27, 2003
Export Citation:
Assignee:
Koninklijke Philips Electronics N.V.
International Classes:
G06F1/10; H03K3/037; H03K5/05; H03K5/15; H03K19/003; (IPC1-7): H03K5/05; H03K3/037
Domestic Patent References:
| JPH1093407A | 1998-04-10 | |||
| JPH0621777A | 1994-01-28 | |||
| JPH10326303A | 1998-12-08 | |||
| JP2001320017A | 2001-11-16 |
Foreign References:
| US5259006A | 1993-11-02 | |||
| US5229657A | 1993-07-20 |
Other References:
中澤喜三郎・中村宏監訳, 「ＶＬＳＩシステム設計」, JPN6008040099, 30 March 1995 (1995-03-30), JP, pages 356 - 363, ISSN: 0001107131
Attorney, Agent or Firm:
Susumu Tsugaru
Akihiko Miyazaki
Fueda Shusen
Akihiko Miyazaki
Fueda Shusen