Title:
INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP2022115310
Kind Code:
A
Abstract:
To inspect the capacity size of a capacitive element provided on a semiconductor substrate without enlarging the area of the semiconductor substrate.SOLUTION: An integrated circuit includes a capacitive element to be inspected Ct_1 and an inspection circuit 10 on the same semiconductor substrate. The inspection circuit 10 includes a capacitive element for inspection Cs_1 and a comparison circuit Cmp that compares the voltage of a node B and the voltage of a signal Vref_B with each other, in a first period, connects the other end of the capacitive element to be inspected Cmp to the node B and applies the voltage of s signal Vref_A to the node B, and in a second period after the first period, based on the capacity ratio between the capacitive element to be inspected Ct_1 and the capacitive element for inspection Cs_1, changes the voltage of the node B, and based on a result of comparison made by the comparison circuit Cmp, inspects the capacity size of the capacitive element to be inspected Ct_1.SELECTED DRAWING: Figure 1
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Inventors:
MORITA AKIRA
UKAI SHINYA
UKAI SHINYA
Application Number:
JP2021011846A
Publication Date:
August 09, 2022
Filing Date:
January 28, 2021
Export Citation:
Assignee:
SEIKO EPSON CORP
International Classes:
H01L21/822; G01R31/28; H01L21/82; H03M1/10; H03M1/80
Attorney, Agent or Firm:
Ochi International Patent Office