PURPOSE: To prevent a drop in the number of IC chips acquired by on-wafer screening inspection using a high frequency needle by employing a layout in which a ground potential supply pattern is arranged on a dicing line.

CONSTITUTION: A layout is employed in which a ground potential supply pattern 103 is arranged on a dicing line 102 between a ground pad 1 and a ground pad 2, between the ground pad 1 and a ground pad 4, and between the ground pad 4 and a ground pad 5. Because of this means, a dicing margin L3 is only left between the pads and the dicing line 102. By arranging the ground potential supply pattern 103 on the dicing line, this supply pattern is eliminated after a wafer has been diced, and hence it becomes possible to make a parasitic capacitance C substantially zero. Thereby, if a corresponding characteristic is assured at the time of on-wafer screening inspection and after the dicing of the wafer, more accurate screening will be possible, and the best characteristics, without the deterioration of a signal, can be derived after an integrated circuit has been assembled.