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Patent Searching and Data


Title:
INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS6367817
Kind Code:
A
Abstract:

PURPOSE: To detect an abnormal rise in the output voltage of a voltage generating circuit by providing an MOSFET which inputs the potential level on wiring as a gate voltage.

CONSTITUTION: The resistance between the drain and source of the MOSFET 11 becomes large and the voltage at an output terminal 12 becomes closer to the ground level (level 0) as a voltage (VCS voltage) which operates a current switching type logic gate (ECL gate), i.e. the voltage on the wiring drops more. As the VCS voltage rises more, on the other hand, the resistance between the drain and source of the MOSFET 11 decreases and the voltage at the output terminal 12 becomes closer to a VEE power source level (level 1). Consequently, when the VCS voltage rises abnormally, the output terminal 12 of the MOSFET 11 is held at the level 1 and the abnormal rise in the VCS voltage is detected.


Inventors:
IWATA TADASHI
Application Number:
JP21314686A
Publication Date:
March 26, 1988
Filing Date:
September 09, 1986
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03K19/003; H03K19/086; (IPC1-7): H03K19/003; H03K19/086
Domestic Patent References:
JPS59171224A1984-09-27
JPS6052517B21985-11-19
JPS54945A1979-01-06
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)