Title:
改良されたI/O整合を有する集積フィルタおよびその製造方法
Document Type and Number:
Japanese Patent JP4700184
Kind Code:
B2
Abstract:
An integrated filter circuit and a method of fabrication are disclosed, wherein the integrated filter (11) has an input and an output parasitic shunt impedance. Input (17) and output (19) electrical components are coupled to the input (14) and output (15) terminals, respectively, to reduce the input and output parasitic shunt impedances. The input and output electrical components each include one of a coil (17,19), a section of transmission line (27,29), a coil (47,49) and tuneable capacitance (46,48) connected in a series tuned circuit, or a coil (37,39) and tuneable capacitance (26,38) connected in a parallel tuned circuit. The integrated filter includes input and output multilayer ceramic integrated coils (58) which may be positioned so that capacitive coupling between the coils substantially cancels inductive coupling therebetween, and/or an interlayer gridded ground wall is positioned between the input and output coils
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Inventors:
One Chan A Gu
Richard Stefan Komlassie
Richard Stefan Komlassie
Application Number:
JP2000330019A
Publication Date:
June 15, 2011
Filing Date:
October 30, 2000
Export Citation:
Assignee:
Freescale Semiconductor, Inc.
International Classes:
H03H9/64; H03H7/01; H03H7/38; H03H9/00; H03H9/145
Domestic Patent References:
| JP8051334A | ||||
| JP9098056A | ||||
| JP2237211A | ||||
| JP3165058A | ||||
| JP10209374A |
Foreign References:
| WO1999023757A1 |
Attorney, Agent or Firm:
Mamoru Kuwagaki