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Title:
INTEGRATED SUBSTRATE BIAS GENERATING CIRCUIT
Document Type and Number:
Japanese Patent JPS56143722
Kind Code:
A
Abstract:

PURPOSE: To increase a substrate bias voltage in absolute value, by using a clamping MOS diode whose threshold voltage is about 0V.

CONSTITUTION: The bias generating circuit consists of oscillating circuit 1, driving circuit 2, coupling capacitor 3, MOS diode 4 substracting a substrate curretn, and clamping MOS diodes 5 and 6. It transistors TR whose amount of a dose is 1.0× 1011cm-2 are used as diodes 5 and 6, threshold voltage VT is 0.1V, point C is calmped at about 0.2V, and the substrate bias voltage is obtained as shown by equation (6) (where VSUB is the bias voltage, VDD the amplitude of the output pulse of circuit 2, and VTS the threshold voltage of the junction diode). Those TRs are connected in series by (n) stages to control the substrate voltage as shown by equation (7) [where (n) is an integer satisfying equation (8)]. Further, VT can be controlled to any value through ion injection.


Inventors:
HIRATA MASAKI
Application Number:
JP4667280A
Publication Date:
November 09, 1981
Filing Date:
April 09, 1980
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H03K19/094; G05F3/20; G11C11/407; H01L21/822; H01L27/04; H03K17/687; (IPC1-7): H03K17/687; H03K19/00
Domestic Patent References:
JPS53121561A1978-10-24
JPS53102682A1978-09-07
JPS54109750A1979-08-28



 
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