Title:
INTEGRATING CIRCUIT
Document Type and Number:
Japanese Patent JP3165053
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide an integrating circuit which suppresses the variance in the saturation voltage of a transistor TR controlling charging of a capacity element and the variance of the temperature at the time of calculating an integration action time.
SOLUTION: A measurement object signal input terminal IN, a constant voltage circuit part VREF 11 which generates a constant voltage, a voltage/ current conversion circuit part IREF 12 which converts the output voltage of the VREF into a current, a capacity element connection terminal CPT which supplies an output current I0 of the IREF 12 to an externally connected capacity element, a voltage comparator CP 13 which has one input connected to the terminal CPT to detect an integrated potential charged in the capacity element and has the other input connected to the measurement object signal input terminal IN and compares these input potentials with each other to output an inverted output voltage to an output end OUT at the time of coincidence between them, and a switching means 14 which has an input end connected to the output end of the VREG 11 and has an output end connected to the terminal CPT and is set to the conductive or non-conductive state in response to a voltage supplied from the outside through a control terminal CTL are provided.
Inventors:
Hiromitsu Iwata
Application Number:
JP1678397A
Publication Date:
May 14, 2001
Filing Date:
January 30, 1997
Export Citation:
Assignee:
NEC IC Microcomputer System Co., Ltd.
International Classes:
G06G7/184; G01R19/255; (IPC1-7): G06G7/184
Domestic Patent References:
| JP561993A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)