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Title:
INTEGRATING SYSTEM FOR NEURAL NETWORK
Document Type and Number:
Japanese Patent JPH04128962
Kind Code:
A
Abstract:

PURPOSE: To make an integrated neural network possible to obtain an accurate output quickly by judging the condition of a signal output from each neurocomputer, by converting the output signal into a semantic digital code that can be treated for arithmetic logical operation, and by obtaining the final integrated output result through the arithmetic logical operation of the output signal.

CONSTITUTION: When carrying out pattern recognition using a neurocomputer, a plurality of neurocomputers prepared in small scale in the beginning are used to obtain partial pattern recognition outputs, and in order to integrate these output results quickly, an output (usually analog signal) from each neurocomputer is converted into a semantic digital code by semantic units 4a-4c, etc. Further, in the integrated unit section 5, a digital code from semantic units 4a-4c is treated for operation integrating processing by means of arithmetic function or logic function. With this, learning can be quickly converged, and when obtaining a result of the final pattern recognition, a pattern recognition output can be obtained accurately.


Inventors:
YOKONO MASAYUKI
Application Number:
JP24891190A
Publication Date:
April 30, 1992
Filing Date:
September 20, 1990
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06G7/60; G06F15/18; G06N3/04; G06N99/00; (IPC1-7): G06F15/18; G06G7/60
Attorney, Agent or Firm:
Takashi Honma



 
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