Title:
INTEGRATOR
Document Type and Number:
Japanese Patent JP2694767
Kind Code:
B2
Abstract:
PURPOSE: To operate the integrator at a low power supply voltage by connecting an amplifier circuit consisting of two differential amplifier circuits to an input side of the integration circuit of an emitter ground type, and connecting an offset eliminating circuit to its amplifier circuit.
CONSTITUTION: Emitters of transistors Q1, Q2 for forming a transistor differential pair of a first differential amplifier circuit A1 are connected to each other and connected to a variable current source S1, and emitters of transistors Q3, Q4 for forming a transistor differential pair of a second differential amplifier circuit A2 are connected to each other and connected to a variable current source S2. To bases of the transistor Q1 and the transistor Q3, an input signal 9 superposed on a bias voltage VBA is applied through a resistance R1, and to bases of the transistor Q2 and the transistor Q4, the bias voltage VBA is applied. Also, an offset eliminating circuit for eliminating an offset generated in the base of the transistor Q1 being an input terminal of the amplifier circuit is connected.
Inventors:
Hiroshi Tanikawa
Application Number:
JP29418593A
Publication Date:
December 24, 1997
Filing Date:
October 29, 1993
Export Citation:
Assignee:
Toko Co., Ltd.
International Classes:
G06G7/184; G06G7/186; (IPC1-7): G06G7/184; G06G7/186
Domestic Patent References:
| JP3144784A |
Attorney, Agent or Firm:
Yu Ota