Title:
INTEGRATOR
Document Type and Number:
Japanese Patent JP3158125
Kind Code:
B2
Abstract:
PURPOSE: To cope with a high input voltage and to obtain sufficient gain by using a passive integrator disposed on an input side, and an active integrator disposed on an output side.
CONSTITUTION: This integrator integrates a signal generated as time elapses with regard to the time, and is provided with a passive integrator 1 disposed on an input side, and an active integrator 3 disposed on an output side. Accordingly, by the passive integrator 1 disposed on the input side, it is possible to cope with an excessive input voltage. Also, by the active integrator 3 disposed on the output side, sufficient gain is obtained, and a degree of freedom of a design is improved. In such a manner, by combining the passive integrator 1 and the active integrator 3, it is possible to cope with a high input voltage, and also, the integrator of high gain can be realized.
Inventors:
Ishioka Ogoro
Application Number:
JP34034091A
Publication Date:
April 23, 2001
Filing Date:
November 28, 1991
Export Citation:
Assignee:
Clarion Co., Ltd.
International Classes:
G06G7/18; G06G7/184; G06G7/186; (IPC1-7): G06G7/184
Domestic Patent References:
| JP5587279A | ||||
| JP1265375A | ||||
| JP1193981A | ||||
| JP5515553A | ||||
| JP51140540A | ||||
| JP6142660U |
Attorney, Agent or Firm:
Kiyoshi Takahashi