INTER-PROCESSOR DATA TRANSFER CIRCUIT

Japanese Patent JPS63276160

A

PURPOSE:To realize the simultaneous transfer of data to plural processors in a simple transfer procedure by using the signal which reads the transmitted data to a processor set at the reception side also as a signal which selects a data receiving processor out of plural processors. CONSTITUTION:When data are transferred to No.3 and 4 processors 3 and 4 from No.1 processor 1, the transfer data is set at an output register 10 of the processor 1 and then delivered to an output gate 11 to output the data to be transferred onto a data line 12. At the same time, a selection strobe instruction is delivered from an instruction register 5 and plural decoder input signals 23 are delivered to a decoder 24. Receiving these signals 23, the decoder 24 decodes a specific processor to transfer data. When both processors 3 and 4 want to transfer data, only the decoder output lines connected to OF terminals 11 and 12 via an AND 26 are set at high levels.

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EGUCHI KOHEI
NOGUCHI OSAMU
MIYAMOTO RYOICHI
KAMOI HIDEKI

JP10969887A

November 14, 1988

May 07, 1987

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OKI ELECTRIC IND CO LTD

G06F15/16; G06F13/38; G06F15/17; G06F15/177; G06F15/80; (IPC1-7): G06F15/16

Toshiaki Suzuki

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