Title:
VITERBI DECODER AND VITERBI DECODING PROCESSING METHOD
Document Type and Number:
Japanese Patent JP3204240
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a Viterbi decoder that is used for an ADSL MODEM and preferably whose circuit configuration can be simplified and to provide a Viterbi decoding processing method.
SOLUTION: A pre-stage of the Viterbi decoding circuit is provided with a Viterbi pre-processing circuit that selects and outputs correction object bits being an object of error correction and soft discrimination data required for the error correction in received constellation coordinate data, with a Viterbi decode circuit 17 that uses the soft discrimination data and an error correction code included in the error correction object bits to correct an error in the correction object bits, with a Viterbi post processing circuit 19 that corrects an error in the coordinate data on the basis of the correction object bits whose error is corrected, and also with a de-mapping circuit that converts the coordinate data whose error is corrected into a bit stream on the basis of a corresponding constellation map.
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Inventors:
Mitsuhiro Ono
Application Number:
JP4063399A
Publication Date:
September 04, 2001
Filing Date:
February 18, 1999
Export Citation:
Assignee:
NEC
International Classes:
H04L1/00; H03M13/23; H03M13/25; H03M13/41; H04J11/00; H04L27/00; (IPC1-7): H03M13/41; H04J11/00; H04L1/00; H04L27/00
Domestic Patent References:
| JP22277A | ||||
| JP7143185A | ||||
| JP11136304A | ||||
| JP897866A | ||||
| JP2001127649A |
Attorney, Agent or Firm:
Masanori Fujimaki