Title:
INTERFACE CIRCUIT, AND TESTING METHOD AND DEBUGGING METHOD USING THE SAME FOR SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3751531
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide an interface circuit capable of reducing its manufacturing cost and accurately performing functional test and debugging by reducing the number of input terminals from the exterior of a miniaturized semiconductor device, and provide a testing method and a debugging method using the same for the semiconductor device.
SOLUTION: A test clock signal TCK, a test reset signal TRST, a test mode select signal TMS, and a serial data input signal TDI are outputted from a protocol converter 102 having received a signal from a host computer 101. Time-division serial signals related to the select signal TMS and input signal TDI are generated by an external signal conversion circuit 107 in the interface circuit 106 and inputted into the semiconductor device 103 via an interface signal terminal 109CD, then divided by an internal signal conversion circuit 108, and transmitted to a TAP controller 105.
Inventors:
Masanori Yamada
Application Number:
JP2001076236A
Publication Date:
March 01, 2006
Filing Date:
March 16, 2001
Export Citation:
Assignee:
Oki Electric Industry Co., Ltd.
International Classes:
G01R31/28; G01R31/317; G01R31/3185; G01R31/319; G06F11/22; (IPC1-7): G01R31/28; G06F11/22
Domestic Patent References:
| JP60117819A | ||||
| JP1217274A | ||||
| JP10209992A |
Attorney, Agent or Firm:
Kenji Onishi