Title:
INTERFACE CIRCUIT
Document Type and Number:
Japanese Patent JP3042568
Kind Code:
B2
Abstract:
PURPOSE: To decrease the number of pins for input/output of an LSI by converting the binary signal of the LSI to a binary-multivalue signal or multivalue-binary signal when it is inputted/outputted.
CONSTITUTION: A CPU chip and a memory chip are comprised of binary logic circuits. A binary address signal handled by a CPU is outputted by converting to a multivalue signal via an I/F2A. An outputted signal is converted to the binary signal via the I/FMA of memory1, and is stored in the memory1. Also, a binary data signal handled by the CPU is outputted by converting to the multivalue signal via a binary-multivalue I/F2A. Outputted multivalue data is converted to binary data via the multivalue-binary conversion I/FMA of a memory1 chip, and is stored in the memory1. In such a way, binary-multivalue conversion is performed via the I/F2D of the memory1 when the data stored in the memory1 in the binary data is processed by the CPU, and multivalue-binary conversion is applied to it via the I/FMD of the CPU, then it is processed by the CPU.
Inventors:
Yang Yasuyasu
Wiwat Wonwalla Wipat
Kotobuki Guoliang
Nao Takatori
Makoto Yamamoto
Wiwat Wonwalla Wipat
Kotobuki Guoliang
Nao Takatori
Makoto Yamamoto
Application Number:
JP30174092A
Publication Date:
May 15, 2000
Filing Date:
October 13, 1992
Export Citation:
Assignee:
Takayama Co., Ltd.
Sharp Corporation
Sharp Corporation
International Classes:
H03K19/0175; H03K19/20; H03M7/02; (IPC1-7): H03K19/0175; H03K19/20
Domestic Patent References:
| JP6126326A | ||||
| JP3116494A |
Attorney, Agent or Firm:
Makoto Yamamoto