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Title:
INTERFACE CONTROL DEVICE
Document Type and Number:
Japanese Patent JPS6155759
Kind Code:
A
Abstract:

PURPOSE: To check a data processing series error and the normality of a detecting function from an external device side of a process control device, etc., by installing an error checking circuit, error inserting circuit and a judging circuit.

CONSTITUTION: Data transfer between the titled device and an external device 106 is executed by an instruction from CPU by using a microprogram control circuit 207 and a ROM208, and the data are checked at an error checking circuit 205. In such a case, the erroneous data can be set intentionally through a signal line 250 to data registers 203 or 204 by using an error inserting circuit 209. At this time, when the circuit 205 is normal, said data is instantaneouly detected, and at a judging circuit 210, a signal received from the circuit 209 decides that it is an error generated, intentionally. The output of the circuit 210 is supplied to the device 106 and it is transmitted that error detecting function is normally operated for an error inserting indication. Thus, the normality of a data processing system error and detecting function are checked from an external device side.


Inventors:
UCHIDA AKIO
Application Number:
JP17891084A
Publication Date:
March 20, 1986
Filing Date:
August 28, 1984
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F11/22; G06F13/00; (IPC1-7): G06F11/22; G06F13/00
Attorney, Agent or Firm:
Naotaka Ide



 
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