PURPOSE: To speed up the interface response processing, by separating the logical section for normal and abnormal processing, comparing an input tag value with an expected value and advancing the stage.

CONSTITUTION: The system consists of a new input tag register 201 setting a sampling input tag signal, old input tag register 202 set previously by one, input tag expected value register 203 to which the prescribed value to be inputted next is set, circuit 205 comparing the input tag with the previous value, matrix logical circuit 214 executing the prescribed processing, output tag register 210 to which a response signal is set, and counters 212, 213 of sequence stage indicating the channel status.