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Patent Searching and Data


Title:
INTERFACE DEVICE OF DIGITAL MULTIPLEX TRANSMISSION LINE
Document Type and Number:
Japanese Patent JPS5912663
Kind Code:
A
Abstract:

PURPOSE: To attain a folded test, by providing a means inverting the logic of an optional output bit of one side of a write address forming counter and an address forming counter with a control signal, for replacing the connection between a channel on a transmission line and that on an exchange.

CONSTITUTION: An output data of a receiving pulse generating circuit of a digital multiplex transmission line interface device is stored once in a frame phase memory 150 and a signal DR in synchronizing with a frame Fr of the exchange is outputted. The write and readout address to the memory 150 is fed in terms of a memory address MAD outputted from an address selector 151. This selector 151 outputs selectively an output of the write address forming counter 152 and the readout address forming counter 153. Further, the logic of an optional output of one of the counters 151, 152 is inverted with a control signal T by means of a frame aligner 102 and a multi-frame aligner 103 and the like of the selector 151 to replace the channel on the transmission line with that on the exchange.


Inventors:
NAKANE HIDEKI
Application Number:
JP12053382A
Publication Date:
January 23, 1984
Filing Date:
July 13, 1982
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H04M3/26; H04J3/14; H04M3/24; (IPC1-7): H04J3/14; H04M3/26
Attorney, Agent or Firm:
Sumita Toshimune